28C datasheet, 28C pdf, 28C data sheet, datasheet, data sheet, pdf, Atmel, K 32K x 8 Paged CMOS E2PROM. 28C Microchip. K (32K x 8) CMOS Electrically Erasable PROM. PIN CONFIGURATION. Top View. A 1 A7. A A *NC. Vcc. WE. [1]. A2. 5 WE. A dimensions section on page 14 of this data sheet. ORDERING INFORMATION. PLCC−32 . 28C− 28C− Units. Min. Max. Min. Max. tRC.

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The device also includes an extra bytes of E. The data in the enable and disable command se- quences is not written to the device and the memory ad- dresses used in the sequence may be written with data in either a byte or page write operation. Hardware and Software Data Protection. Its K of memory is organized as 32, words by 8 bits. It should be noted, that once protected the host may still perform a byte or page write to the AT28C For each WE high to low transition during the page write operation, A6 – A14 must be the same.

The page write operation of the AT28C allows 1 to bytes of data to be written into the device during a single internal programming period.

Please see Soft- ware Chip Erase application note for details.

The device utilizes internal error correction for extended endurance and improved data retention characteristics. Exposure to absolute datasehet rating conditions for extended periods may affect device reliability.

When the device is deselected, the CMOS standby current is less than PROM for device identification or tracking. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes.


Input Test Waveforms and Measurement Level. If precautions are not taken, inad- vertent writes may occur during transitions of the host sys- tem power supply. The datashete device can be erased using a 6-byte software code.

Fast Write Cycle Times.

28C (ATMEL) – k 32k X 8 Paged Cmos E2prom | eet

The A0 to A5 inputs are used to specify which bytes within the page are to be written. Hardware features protect against inadvertent writes to the AT28C in the follow- ing ways: By raising A9 to 12V. Once a byte write has been started it datasheey automatically time itself to completion. A software controlled data protection feature has been implemented on the AT28C Once a programming operation has been initiated and for the duration of t.

SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses refer to Software Data Protection Algorithm. No data will be written to the device; however, for the duration of t. Once the write cycle datashset been completed, true data is valid on all outputs, and the next write cycle may begin.

Manufac- tured with Datasueet advanced nonvolatile CMOS technology, the device offers access times to ns with power dissipation of just mW.

28C256 Datasheet PDF

The address is latched on the falling edge of CE or WE, whichever occurs last. All bytes dur- ing a page write operation must reside on the same page as defined by the state of the A6 – A14 inputs.


An optional software data protection mechanism is available to guard against inad- vertent writes.

PROM memory are available to the user for device. OE may be delayed up to t. DATA Polling may begin at anytime during the write cycle. CE to Output Delay.

28C256 – 28C256 256K 250ns Parallel EEPROM Technical Data

After setting SDP, any attempt to write to the device with- out the 3-byte command sequence will start the internal write timers. During a write cycle, the addresses and 1 to bytes of data are internally latched, freeing the address and data bus for other opera- tions. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur.

The device contains a byte page register to allow writ- ing of up to bytes simultaneously. The bytes may be loaded in any order and may be altered within the same load period.

All command se- quences must conform to the page write timing specifica- tions. Reading the toggle bit may begin at any time during the write cycle. 228c256 the initiation of a write cycle, the device will automatically write the latched data using an internal control timer.

The outputs are put in the high impedance state when either CE or OE is high.